MyHDL: design hardware with Python
MyHDL is a free and open-source package that turns Python into a hardware description and verification language. Python is a high level concise and dynamic language that can provide hardware engineers with unique power to model and simulate their designs.
Digital hardware design is usually developed in a specialized language that is called a hardware description language (HDL). The most widely used HDLs are Verilog and VHDL. MyHDL has Verilog and VHDL converter that introduces a way into a traditional design flow, including synthesis and implementation. Python's power and clarity is what makes it perfect as a language to directly design hardware in. It allows hardware designers to benefit from a popular high-level programming language and its open-source model.
The use of Verilog or VHDL depends on the regions and sectors, but is mainly equal, so it is useful to have design available in both languages. Using MyHDL design and high-quality automatic conversion to produce equivalent code in both Verilog and VHDL is one of the best solutions for language-neutral design. It is much better option than manual and direct conversion between Verilog and VHDL.
MyHDL uses Python generators (similar to Verilog blocks and VHDL processes) to model hardware concurrency, while a hardware module is a function that returns generators. It enables support of such features as conditional instantiation, named port association, arrays of instances, and arbitrary hierarchy. Moreover, MyHDL has classes that provide implementation of traditional hardware description concepts, like support of communication between generators, enumeration types, or support of bit oriented operations.
Advantages of using MyHDL
Python/MyHDL aids in the unification of the two domains in the same environment. On the one hand, HDL designer can explore algorithm and model design, on the other hand, an algorithm or model designer can explore HDL implementation. With the knowledge of HDL-based design and robust Python environment the conversion from algorithm to an HDL is easier, quicker and increases productivity.
Main features of MyHDL are the capability to convert output verification and a lists of signals, capability to generate a testbench with test vectors and code from a MyHDL design in both VHDL and Verilog code. Also MyHDL has an advanced datatype system, independent of traditional datatypes, and translator tool that automatically writes conversion functions when the target language requires them.
MyHDL allows to use a Python unit test framework to do test-driven development for hardware design. Although it is a common software verification technique, unit testing is still rarely used in the hardware design world. At the same time MyHDL has the built-in simulator that runs on top of the Python interpreter and supports waveform viewing.
MyHDL as a Python based HDL is a perfect solution for high level modeling. Install it and enjoy the Python ecosystem immediately. For more information visit myhdl.org.